1. Field of the Invention
The present invention relates to a phase-locked loop, and more particularly, to a phase-locked loop with nonlinear phase-error response characteristic.
2. Description of the Prior Art
Please refer to FIG. 1, which is a functional block diagram of a conventional analog phase-locked loop (PLL) 10. The PLL 10 comprises a phase/frequency detector (PFD) 12, a charge pump (CP) 14, a charge control circuit 16, a voltage-controlled oscillator (VCO) 18, and a frequency divider 20. The PFD 12 compares a reference signal and a feedback signal generated by the frequency divider 20, and generates a phase error signal, whose magnitude is proportional to a phase/frequency difference between the reference signal and the feedback signal. The CP 14 charges/discharges the charge control circuit 16 according to the phase error signal. The charge control circuit 16 generates a control voltage signal in accordance with the charges stored by the charge control circuit 16. The VCO 18 generates an output signal according to the control voltage signal, the output signal having a frequency proportional to a magnitude of the control voltage signal. The frequency divider 20 divides the output signal output from the VCO 18 and outputs the feedback signal to the PFD 12.
A conventional PLL's 10 phase-error response characteristic, i.e. a corresponding relation between the phase error signal and the output signal, is usually linear. In some circumstances and applications, the PLL's 10 phase-error response characteristic is nonlinear, as shown in FIG. 2 and FIG. 3, and this is usually done by the charge control circuit 16. However, the charge control circuit 16 of the conventional PLL 10 can't be adjusted adaptively because the components thereof such as the resistor and the capacitor shown in FIG. 1 have fixed characteristics. Moreover, due to the process variation and other unexpected factors, the characteristics of electronic components of the analog PLL 10 differ significantly, and the phase-error response characteristic of the analog PLL 10 is therefore neither controllable nor predictable.